• 32/64 bit, +3.3 V PCI / PCI - X -based PWB
  • Available in configurations with two to five Stratix™ EP1S80 FPGA s (1508 BGA )
  • Four external 512 k x 36 SSRAMs
    • Pipeline, flowthrough or ZBT
    • Supports up to 2 M X 36 SSRAM s
  • One external 72-bit SDRAM DIMM
    • Ships standard with a 512 MB SDRAM DIMM
    • Supports up to 8 GB SDRAM DIMM
  • Tightly interconnected FPGA s facilitate the partitioning process.
  • Status LED s provide instant status and operational feedback.
  • Flexible, abundant and configurable embedded memory in FPGA s:
    • 4.6 MB dual-port ESB RAM blocks (assuming five 1S80s.
  • Two CY7B993/4 RoboclockII PLLs
  • Two FCT3807 Clock Drivers
  • +10 A switching regulator for both +3.3 V and +1.5 V (only requires +5 V power).
  • Standalone operation via separate power connector
  • Fast/Easy FPGA configuration via standard SmartMedia FLASH card
    • Microprocessor controlled (ATmega128L)
    • RS232 port for configuration/operational status and control
    • Fastest possible configuration using parallel bus
    • Five 1A80s configures in less than 5 seconds
    • Sanity checking programs for bit files simplify the configuration process
  • 5low skew clocks distributed to all FPGA s and headers (from up to 8 possible sources)
    • 2 user-selectable socketed oscillators
    • PCI / PCI - X clock
    • 1 dividable clock via CPLD
    • 4 external clocks via ribbon cable (may be differential!)
  • Robust observation/debug with 485+ connectors for logic analyzer observability and pattern generator stimulus
  • Custom daughter PWB headers for application-specific circuitry and interfaces.

  • Product Brief - PDF[HI - 18.5MB][LO - 307KB]
  • User Manual [PDF - 6.1MB]
  • Data Sheet [PDF - 922KB]
  • Interconnection Table [PDF - 16KB]
  • Stuffing Options [PDF - 5KB]
  • Altera Stratix Errata [PDF - 206KB]
  • Daughter Card Compatibility Guide [PDF - 65KB]
  • AETEST Utility
  • 200-pin Header Connection Summary [XLS - 2.7MB]

 

DN5000k10
Stratix-Based
ASIC Prototyping Engine

The DN5000k10 is a complete logic emulation system that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of other solutions. The DN5000k10 is also applicable to algorithmic acceleration and reconfigurable computing. The DN5000k10 can be hosted in a 32/64 bit PCI / PCI - X slot, or can be used standalone. A single DN5000k10 configured with five 1S80s can emulate up to 3–4 million gates of logic as measured by LSI (not including memories, multipliers, and DSP functions). The DN5000k10 achieves high gate density and allows for fast memory. High I / O count, 1508-pin, flip-chip BGA packages are employed providing for abundant, fixed interconnect between the FPGA s. A total of 485 test pins are provided on the top of the PWB for logic analyzer-based debugging, or for pattern generator stimulus. Custom daughter cards can be mounted to these connectors as a means of interfacing the DN5000k10 to application-specific circuits. A reference 32-bit PCI target design and test bench is provided (in Verilog/ VHDL ) at no additional cost.

Easy Configuration Via SmartMedia

The configuration bit files for the FPGA s are copied onto a SmartMedia FLASH card (provided) and an on-board ATmega128L microprocessor controls the FPGA configuration process. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. Quick FPGA configuration occurs at the fastest possible parallel frequency. Eight LED s provide instant status and operational feedback. Two of these LED s are connected to the CPLD and are userconfigurable.

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