• PCI Express (4-lane) logic prototyping system with 2-6 Xilinx Virtex-5 FPGA's
    • XC5VLX330-1, -2 (FF1760)
  • Genesys Logic GL9714 PCI Express Physical Interface (PCIe GEN1 rev 1.1)
    • Standard 250MHz or 125MHz PIPE interface between PHY and FPGA A
  • 100% FPGA resources available for user application
  • Nearly 12M ASIC gates (LSI measure) with 6 LX330s
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450Mhz LVDS chip to chip (slightly slower single-ended)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) connects all LX FPGAs (160 signals)
    • Single-ended
  • Auspy models for automatic partitioning
  • 6 separate DDR2 SODIMMs (250MHz)
    • 1 SODIMM for FPGAs A,B,F,D
    • 2 SODIMMs for FPGA C
    • 64-bit data width, 250MHz operation
    • PC2-4200 or better
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32.0Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • SRAM: QDR, ASYNC, STD, or PSRAM
      • FLASH
      • DRAM: SDR, DDR1, PSRAM or RLDRAM
      • Mictor
      • Extra Interconnect
  • SODIMM Daughtercard expansion
  • Eight independent low-skew global clock networks
    • G0, G1, G2, M48, EXT0, EXT1, FBB, FBE
    • Three high-resolution user-programmable synthesizers for G0, G1, G2
      • User configurable via CompactFLASH or USB
    • Global clocks networks distributed differentially and balanced
    • Three independent single-step clocks
    • Up to three independent external clock inputs (single-ended or differential) can be injected onto low-skew global clock networks
  • Flexible customization via daughter cards
  • Fast and Painless FPGA configuration
    • CompactFLASH, JTAG, and USB
    • Configuration Error reporting
    • Accelerated configuration readback
  • RS232 port for embedded uP debug
    • Accessible from all FPGAs
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro
  • 130 status LEDs: enough to tan a small giraffe (LGTA)

    • DN9000K10PCIe-4GL Product Brief - PDF[HI - 6.32MB|LO - 670KB]
    • DN9000K10PCIe-4GL LX330 Block Diagram - PDF - 859KB
    • DN9000K10PCIe-4GL LX110/LX220 Block Diagram - PDF - 866KB
    • DN9000K10PCIe-4GL User Manual - PDF - 5.79MB
    • DN9000K10PCIe-4GL Errata - PDF - 46KB
    • MEG Array Daughter Card Interface Description [PDF - 660KB]
    • Daughter Card Compatibility Guide [PDF - 63KB]
    • QL5064_INTERFACE Module Description and Usage [PDF - 357KB]
    • Dini Group Mainbus Specification [PDF - 167KB]
    • Dini Group USB Specification [ZIP - 180KB]
    • Downloads Page

     

    DN9000K10PCIe-4GL
    Xilinx Virtex-5 Based ASIC Prototyping Engine

    Overview
    The DN9000k10PCIe-4GL is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype PCIe-based logic and memory designs for a fraction of the cost of existing solutions. The DN9000k10PCIe-4GL is hosted on a 4-lane PCIe bus, but can be used stand-alone and configured via USB and/or Compact FLASH. A single DN9000k10PCIe-4GL configured with 6 Xilinx Virtex-5, XC5VLX330’s can emulate up to 12 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASIC’s). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to the user application. The DN9000k10PCIe-4GL achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGA’s can be stuffed along with any combination of speed grades.

    Virtex-5 FPGAs from Xilinx
    The DN9000k10PCIe-4GL uses high I/O-count, 1760-pin, flip-chip BGA packages from the ‘LX’ family. A Genesys Logic GL9714 PHY device provides the PCI Express interface. Virtex-5 GTP "RocketIO" is not used. For PCIe applications the user must supply a 1-lane or 4-lane PCIe core in FPGA A. A PCIe power cable is necessary (provided) since a 4-lane PCIe connector cannot provide enough power to satisfy the current-hungry LX330’s. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of each FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 450MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 160-pin main bus (MB) is connected to all FPGA’s including the Spartan configuration FPGA.

    Daughter cards
    Three separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 450MHz (900 Mb/s). Clocks, resets, and presence detection, along with abundant power are included in each connector.

    Memory
    Six separate DDR2 SODIMM sockets are stuffed and have connections to FPGA’s A, B, D, F, and C (two separate sets). Each socket is tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM’s (PC2-4200 or better) work nicely and we can provide these for a small charge. We have developed alternative SODIMM’s that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors and other

    Easy Configuration Via CompactFLASH or USB
    The configuration bit files for the FPGA's are copied onto a CompactFLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs at the fastest possible SelectMap frequency - 48MHz. Multiple LED's provide instant status and operational feedback. As always, reference material such as DDR2 SDRAM controllers, and flash controllers are included (in Verilog, VHDL, C) at no additional cost.

    Status LEDs, Debug
    Although no animal testing was performed, sophisticated statistical models are showing that the 130 status LED’s is enough to tan a small laboratory giraffe. These LED’s are user controllable from the FPGA’s so can be used as visual feedback in addition to the lab giraffe-tanning application (LGTA). A JTAG connector provides an interface to Chipscope and other third party debug tools. Other FPGA debug solutions will be available later in ‘07.

    Specs of FPGAs Avaliable on the DN9000K10