• PCI Express (8-lane) logic prototyping system with 2-6 Xilinx Virtex-5 FPGA's
    • XC5VLX330-1, -2 (FF1760)
  • Xilinx Virtex-5T for PCIe interface and controller
    • PCIe GEN1 rev 1.1 with LX50T
    • PCIe GEN2 coming in 2008
  • 100% FPGA interconnect is single-ended or LVDS
  • Nearly 12M ASIC gates (LSI measure) with 6 Virtex-5 LX330’s
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450Mhz LVDS chip to chip (900 MB/s)
    • Slightly slower when used single-ended (~225MHz)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
  • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) connects all LX FPGA’s (164 signals)
    • Single-ended
  • Auspy models for partitioning assistance
  • 6 separate DDR2 SODIMMs (250MHz)
    • 1 SODIMM for FPGA’s A,B,F,D
    • 2 SODIMM’s for FPGA’s C
    • 64-bit data width, 250MHz operation
    • PC2-4200 or better
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • SRAM: QDR, ASYNC, STD, or PSRAM
      • FLASH
      • DRAM: SDR, DDR1, PSRAM or RLDRAM
      • Mictor
      • Extra Interconnect
  • SODIMM Daughtercard expansion
  • Eight independent low-skew global clock networks
    • G0, G1, G2, M48, EXT0, EXT1, FBB, FBE, REF250
    • Three, high-resolution, user-programmable synthesizers for G0, G1, G2
    • User configurable via CompactFLASH, USB, and/or PCIe
    • Global clocks networks distributed differentially and balanced
  • Three independent single-step clocks
    • Up to three independent external clocks inputs (single-ended or differential) can be injected onto low-skew global clock networks
  • Flexible customization via daughter cards
  • Fast and Painless FPGA configuration
    • CompactFLASH, USB, PCIe, JTAG
    • Configuration Error reporting
    • Accelerated configuration readback
  • RS232 port for embedded uP debug
    • Accessible from all FPGA’s via separate 2-signal bus
  • Full support for embedded logic analyzers via JTAG interface
    • ChipScope, ChipScope Pro
  • 90 status LED’s: enough illumination to disturb the circadian cycle of a Sun fish (DCCSF).

    • DN9000K10PCIe-8T Product Brief [PDF - 723KB]
    • DN9000K10PCIe-8T Product Brief (Hi Res) [PDF - 7.6MB]
    • DN9000K10PCIe-8T Block Diagram [PDF - 554KB]
    • DN9000K10PCIe-8T User Manual [PDF - 3.68MB]
    • PCIE8T Interface User Manual [PDF - 71.5KB]
    • MEG Array Daughter Card Interface Description [PDF - 660KB]
    • Daughter Card Compatibility Guide [PDF - 63KB]
    • Dini Group Mainbus Specification [PDF - 167KB]
    • Dini Group USB Specification [ZIP - 180KB]
    • Downloads Page

     

    DN9000K10PCIe-8T
    Xilinx Virtex-5 Based ASIC Prototyping Engine

    Overview
    The DN9000k10PCIe-8T is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype PCIe-based logic and memory designs for a fraction of the cost of existing solutions. The DN9000k10PCIe-8T is hosted in an 8-lane PCIe bus, but can be used stand-alone and configured via USB and/or Compact FLASH. A single DN9000k10PCIe-8T configured with 6 Xilinx Virtex-5, XC5VLX330’s can emulate up to 12 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASIC’s). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to the user application. The DN9000k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing the largest FPGA from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGA’s can be stuffed along with any combination of speed grades.

    Dedicated Virtex-5T FPGA for PCIe, 8-lane controller
    A Xilinx Virtex-5 LX50T FPGA is used to host the PCI Express controller. We ship a full function, fixed, 8-lane master/target with the product, along with drivers and ‘C’ source for several operating systems. The user can use this FPGA for emulating his/her own controller or third-party IP.

    Virtex-5 FPGAs from Xilinx
    The DN9000k10PCIe-8T uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of both FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 450MHz+ (which is 900 Mb/s if used in DDR mode). Single-ended at the reduced speed of 225MHz is characterized and tested. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 182-pin main bus (MB) is connected to all FPGAs including the Spartan configuration FPGA, allowing for data movement via USB.

    Daughter cards
    Three separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially and can run at the limit of the FPGA: 450MHz. Clocks, resets, and presence detection, along with abundant power are included in each connector. Two adjacent MEG-Array connectors can be converted to FPGA to FPGA interconnect with a DNMEG_Intercon.

    Memory
    Six separate DDR2 SODIMM sockets are stuffed and have connections to FPGA’s A, B, D, F, and C (two separate sets). Each socket is tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM’s (PC2-4200 or better) work nicely and we can provide these for a small charge. We have developed alternative SODIMM’s that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors, USB PHYs, DDR3, and others.

    Easy Configuration via Compact FLASH, PCIe or USB
    The configuration bit files for the FPGA's are copied onto a Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface or downloaded via PCIe. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs over the highest-speed parallel SelectMap interface. Multiple LED's provide instant status and operational feedback. As always, reference material such as a DDR2 SDRAM controller is included (in Verilog, VHDL) at no additional cost.

    Status LED’s, Debug
    Although no animal testing was performed, sophisticated statistical models are showing that the 90 status LED’s is enough to disturb the circadian cycle of an elderly Sun fish (DCCSF). Please don’t try this at home – the fish tend to get quite testy when their sleep cycles are altered. These LED’s are user controllable from the FPGA’s so can be used as visual feedback in addition to irritating large, bizarre fish. A JTAG connector provides an interface to Chipscope and other third party debug tools. Other FPGA debug solutions will be available later in ‘07.

    Specs of FPGAs Avaliable on the DN9000K10PCIe-8T