• PCIe controller using Xilinx Virtex-5 LX50T FPGA
    • 8-lane PCIe (using GTP’s)
      • 2.5 Gb/s per lane with Virtex-5 LXT (GEN1)
      • 5.0 Gb/s per lane planned 2008
    • Multiple options for PCIe controller
      • User supplied (for ASIC and SOC prototyping)
      • Fixed target/master (shipped with board)
      • Configuration via dedicated Flash,CompactFlash, or USB
  • One or two Xilinx Virtex-5 FPGAs
    • XC5VLX110, XC5VLX220, or XC5VLX330 (FF1760)
    • 100% FPGA resources available for user application
    • Nearly 4 million ASIC gates (LSI measure) with two LX330's
      • Another 276k gates in LX50T
      • 443,520 FF’s with 2 LX330s and 1 LX50T
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450Mhz LVDS chip to chip (900mbps DDR)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) -- 36 signals
    • Single-ended
    • Connects to both V5 FPGAs and Spartan Configuration FPGA
  • DDR2 SODIMM (200MHz) on FPGA B
    • 64-bit data width, 200MHz operation
    • Standard PC2-3200/PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR3, interconnect
  • SODIMM Daughtercard expansion
  • 3 board-level global clock networks (GCLK0, GCLK1, GCLK2)
    • Separate programmable synthesizers(Si5326) for each network
      • User configurable via CompactFlash, USB, or PCIe
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available on each global clock network
  • Flexible customization via daughter cards
    • Two, 400-pin Meg-Array connectors (FCI)
    • 93 LVDS pairs + clocks (or 186 single-ended) assuming LX330
    • 450MHz on all signals with LVDS
    • Signal voltage set by daughter card
    • Supplied power rails (fused):
      • +12v (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
    • Convert MEG-Array connectors to FPGA interconnect with DNMEG_Intercon
    • Other MEG-Array daughter cards
  • Fast and Painless FPGA configuration
    • CompactFlash, PCIe, USB or JTAG
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • Full support for embedded logic analyzers via JTAG interface
  • Interconnect models for Auspy partitioning tools
  • 40 status LED's
    • Enough illumination to attract and confuse a Lopper Moth (Pingasa chlora)
  • Now 100% RoHS!
  • Emulate PCIe bridges with DNMEG_cPCIe

  • DN9002K10PCIe-8T Product Brief - PDF[[LO - 506KB]
  • DN9002K10PCIe-8T Block Diagram - [PDF - 508KB]
  • DN9002K10PCIe-8T Manual - [PDF - 3.31MB]
  • DN9002K10PCIe-8T Errata - [PDF - 46KB]
  • PCIE8T Interface User Manual [PDF - 71.5KB]
  • MEG Array Daughter Card Interface Description [PDF - 660KB]
  • Daughter Card Compatibility Guide [PDF - 63KB]
  • Dini Group Mainbus Specification [PDF - 167KB]
  • Dini Group USB Specification [ZIP - 180KB]
  • Downloads Page

 

DN9002K10PCIe-8T
Xilinx Virtex-5 Based ASIC Prototyping Engine

Overview
The DN9002k10PCIe-8T is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9002k10PCIe-8T is hosted in an 8-lane PCIe slot or can be used stand-alone and configured via USB or Compact FLASH. A single DN9002k10PCIe-8T configured with 2 Xilinx Virtex-5, XC5VLX330s can emulate up to 4 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASICs). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to user application. The DN9002k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed.

Dedicated Virtex-5T FPGA for PCIe controller
A Xilinx Virtex-5 LX50T FPGA is used to host the PCI Express controller. We ship a full function, fixed, 8-lane master/target with the product, along with drivers and ‘C’ source for several operating systems. The user can use this FPGA for emulating his/her own controller or third-party IP.

Virtex-5 FPGAs from Xilinx
The DN9002k10 uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of both FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 450MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 36-pin main bus (MB) is connected to both FPGAs including the Spartan configuration FPGA, allowing for data movement via USB.

Daughter cards
Two separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 450MHz. Clocks, and resets along with abundant power are included in each connector. The two MEG-Array connectors can be converted to FPGA to FPGA interconnect with a DNMEG_Intercon.

Memory
A single DDR2 SODIMM socket is stuffed and is connected to FPGA B. The socket is tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory SODIMMs (PC2-4200) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes Flash, SSRAM, QDR SSRAM, mictors, DDR3, interconnect, and others.

Easy Configuration Via CompactFlash or USB
The configuration bit files for the FPGA's are copied onto a Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. Multiple LED's provide instant status and operational feedback.

As always, reference material such as DDR SDRAM controller included (in Verilog, VHDL) at no additional cost.

Specs of FPGAs Avaliable on the DN9002K10PCIe-8T