• PCIe controller using Xilinx Virtex-5 LX50T FPGA
    • 8-lane PCIe (using GTP's)
      • 2.5 Gb/s per lane with Virtex-5 LXT (GEN1)
      • 5.0 Gb/s per lane with Virtex-5 FXT (GEN2)
    • Multiple options for PCIe controller
      • User supplied (for ASIC and SOC prototyping)
      • Fixed target/master (shipped with board)
      • Configuration via dedicated Flash, Compact Flash, or USB
  • One or two Xilinx Virtex-5 FPGAs
    • LX110, LX155, LX220, or LX330 (FF1760)
    • 100% FPGA resources available for user application
    • Nearly 4 million ASIC gates (LSI measure) with two LX330's
      • Another 276k gates in LX50T
      • 443,520 FF's with 2 LX330s and 1 LX50T
  • FPGA to FPGA interconnect is single-ended or LVDS
    • 450Mhz LVDS chip to chip (900mb/s)
    • Reference designs for integrated I/O pad ISERDES/OSERDES
      • 10x pin multiplexing per LVDS pair
    • Greatly simplified logic partitioning
    • Source synchronous clocking for LVDS
  • Main Bus (MB) -- 36 signals
    • Single-ended
    • Connects to both V5 FPGAs and Spartan Configuration FPGA
  • Two DDR2 SODIMM (250MHz)
    • 64-bit data width, 200MHz operation
    • PC2-4200
    • Addressing/power to support 4GB in each socket
    • DDR2 Verilog/VHDL reference design provided (no charge)
    • DDR2 SODIMM data transfer rate: 32Gb/s
    • Alternate pin compatible memory cards available (consult factory for availability):
      • QDR SSRAM, FLASH, SSRAM, RLDRAM, Mictor, DDR3, interconnect
  • SODIMM Daughtercard expansion
  • 3 board-level global clock networks (GCLK0, GCLK1, GCLK2)
    • Separate programmable synthesizers (Si5326) for each network
      • User configurable via Compact Flash, USB, or PCI Express
    • Global clocks networks distributed differentially and balanced
    • Single-step clocking available
  • Flexible customization via daughter cards
    • Three, 400-pin MEG-Array connectors (FCI)
      • Two connectors on bottom and one on top
    • 93 LVDS pairs + clocks (or 186 single-ended) assuming LX330
    • 450MHz on all signals with LVDS
    • Signal voltage set by daughter card
    • Supplied power rails (fused):
      • +12V (24W max)
      • +5V (10W max)
      • +3.3V (10W max)
    • Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)
    • Convert MEG-Array connectors to FPGA interconnect with DNMEG_Intercon
    • Other MEG-Array daughter cards
  • Fast and painless FPGA configuration
    • CompactFlash, PCI Express, USB, or JTAG
    • Integrated sanity checks on configuration files
    • Accelerated configuration readback
  • Full support for embedded logic analyzers via JTAG interface
  • Interconnect models for Auspy partitioning tools
  • 48 user-controlled status LED's
    • 24 connected to FPGA A
    • 24 connected to FPGA B
    • enough illumination to perform cosmetic hair removal
  • Now 100% RoHS!
  • Emulate PCIe bridges with DNMEG V5T PCIe
  • Easy PCIe core prototyping with our exclusive PCIe PIPE Slowdown core

  • DN9200K10PCIe-8T Product Brief [PDF Lo - 415KB | Hi - 1.6MB]
  • DN9200K10PCIe-8T Block Diagram - [PDF - 923KB]
  • DN9200K10PCIe-8T Manual - [PDF - 5MB | Français - 5MB]
  • PCIE8T Interface User Manual [PDF - 71.5KB]
  • MEG Array Daughter Card Interface Description [PDF - 660KB]
  • Daughter Card Compatibility Guide [PDF - 63KB]
  • Dini Group Mainbus Specification [PDF - 167KB]
  • Dini Group USB Specification [ZIP - 180KB]
  • Downloads Page

 

DN9200K10PCIe-8T
8-lane PCI Express ASIC Prototyping Board with Virtex-5 FPGAs

Overview
The DN9200k10PCIe-8T is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN9200k10PCIe-8T is hosted in an 8-lane PCIe slot or can be used stand-alone and configured via USB or Compact FLASH. A single DN9200k10PCIe-8T configured with 2 Xilinx Virtex-5, XC5VLX330s can emulate up to 4 million gates of logic as measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASICs). This number does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available to user application. The DN9200k10PCIe-8T achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGAs can be stuffed.

Dedicated Virtex-5T FPGA for PCIe controller
A Xilinx Virtex-5 LX50T FPGA is used to host the PCI Express controller. We ship a fixed, 8-lane master/target with the product for free, along with drivers and 'C' source for several operating systems. It supports two-channel DMA at the maximum PCI Express speeds. Alternatively, the user can use this FPGA for emulating his/her own controller or third-party IP.

Virtex-5 FPGAs from Xilinx
The DN9200k10 uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either differential or single-ended) are provided between the FPGA's. All pins of all banks of both FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 450MHz+ (900 Mb/s in DDR mode) but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A trivial-to-implement MainBus interface is connected to both FPGAs allowing each FPGA to communicate over USB or PCI Express without any IP required.

Daughter cards
Three separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Two of these daughter connectors are on the bottom of the PWB, and one on the top. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 450MHz. Clocks, and resets, along with abundant power are included in each connector. The two MEG-Array connectors on the bottom can be converted to FPGA to FPGA interconnect with a DNMEG_Intercon.

Memory
Two DDR2 SODIMM sockets are stuffed, one connected to each FPGA. The sockets are tested to 250MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMMs (PC2-4200) work nicely and we can provide these for a small charge. We have developed alternative SODIMMs that can be stuffed into these positions. Consult the factory for more details, but the list includes Flash, DDR2, SSRAM, QDR SSRAM, mictors, DDR3, interconnect, single data rate DRAM, USB Phy, and others.

Easy Configuration via Compact FLASH, PCIe, or USB
The configuration bit files for the FPGA's are copied onto a CompactFlash card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface or PCIe. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process and making it extremely fast. Multiple LED's provide instant status and operational feedback. As always, reference material such as DDR SDRAM controller included (in Verilog, VHDL) at no additional cost.

Specs of FPGAs Avaliable on the DN9200K10PCIe-8T