• Camera Link Interface
    • 5 channels input
    • 6 channels output
    • 26-pin MDR connectors
  • Xilinx VirtexII-Pro FPGA
    • 2vp20, 2vp30, 2vp40, or 2vp50
    • –5, -6, or –7
    • 1152 BGA package
  • 200-pin connector for high-speed mating to:
    • DN3000k10/S
    • DN5000k10/S
    • DN6000k10/S/SE/SC/PCI/PCIe
    • DN8000k10PCI/PCIe/PSX
  • Can operate stand-alone
  • 8 Channels RocketI/O (TX/RX)
    • SMB connectors (4 per channel)
    • High-speed serial to 3.125 GB/s per channel
      • With –6 or –7 speed grade FPGA
  • RS232 ports for PowerPC processor visibility
    • 2 Tx/Rx, 1 Tx only
  • Video Input Processor (9-bit)
    • NXP SAA7113H
    • I2C Connection to FPGA
      • PowerPC Setup/Configuration
    • Two PowerPC 405 Cores (in FPGA)
      • Embedded 300+ MHz Harvard Architecture
      • Hardware Multiply/Divide Unit
      • Thirty-Two 32-bit General Purpose Registers
      • 16 KB 2-Way Set-Associative Instruction Cache
      • 16 KB 2-Way Set-Associative Data Cache
      • Memory Management Unit (MMU)
      • Timer Facilities
    • Full support for embedded logic analyzers (via JTAG)
      • ChipScope, ChipScope PRO
      • Self contained power
        • Only an external +5V is required
      • 2 Programmable Clock Generators
        • ICS8442
      • 24 pairs (or 48 single-ended) High Speed I/O
        • Selectable Vref
        • Selectable VCCio
    • Block Diagram - [PDF - 250KB]
    • Product Brief - PDF [HI - 3.8MB| LO - 308KB]
    • Daughter Card Compatibility Guide [PDF - 65KB]
    • 200-pin Header Connection Summary [XLS - 2.7MB]

 

Camera Link / LVDS Card
VirtexII™-Pro Based
Camera Control System

The LVDS/Camera Link Interface supports 5 input channels of Camera Link and 6 output channels as defined by the Camera Link specification (October 2000). High performance LVDS interface chips from National Semiconductor are used on the interface making for robust, high-speed connections. The Camera Link MDR26 cables are mounted directly to the circuit board. If Camera Link is not required, a custom cable package is available that allows the construction of custom cables. This allows the use of any or all of the LVDS interfaces for other purposes. A Xilinx VirtexII-Pro FPGA is used as an interface chip and 100% of the FPGAs resources are available for user application. Data is transferred through the FPGA to the ASIC Emulation host through a standard 200-pin connector and/or through 8 separate, bi-directional RocketI/O (MGT) channels. A video input channel, based on the NXP SAA7113H, is used to digitize a composite video signal.

This product is intended to be a peripheral to any of The DINI Groups ASIC emulation products, but can be used stand-alone.