NEW YORK — Designers
should be aware of several "gotcha's" that can impede designs
moving from ASICs to FPGAs, said Mike Dini of The Dini Group
in a presentation Wednesday (Nov. 6) at the SoC Online
conference, sponsored by EE Times.
Dini detailed the obstacles to such a conversion, compared
today's main FPGA architectures and gave his take on the tools
available for FPGA designs.
"I'm going to get some flack for this, but I believe that
there are only two major vendors that have large and fast
FPGAs for considering migrating ASICs to FPGAs — they are
Xilinx and Altera," said Dini, an ASIC and FPGA design
consultant.
The "gotcha's" can surprise designers regardless of which
vendor's FPGA is chosen, Dini said. They involve an FPGA's use
of clocks, memories and multiplexers, and the DesignWare tools
written for the FPGA.
FPGAs have from four to 16 fixed clocks per device, Dini
said. "You can't use routed clocks since that would put too
much strain on clock skew and work to your disadvantage," he
said. Low-power applications, which typically employ many
gated clocks, should move all clock gating into a single
module, he said. Dini also cautioned against using FPGAs to
prototype power management circuits, because "when FPGAs lose
power they lose their brains," he said.
A second gotcha is that FPGAs use a different memory
structure than ASICs. "In most cases you can write an RTL
wrapper to make the FPGA embedded memory behave identically to
the ASIC memory," Dini advised.
For multiplexing, Dini said that SRAM-based FPGAs don't do
the task well, and that not much can be done about this. "We
have tried to rewrite the code to suit multiplexing functions,
but have not been very successful," he said.
A final irritant about FPGAs is the lack of DesignWare
libraries for them. "They are simply not available and the
Synopsys ones don't translate the RTL to the hardware very
well," he said.
Low marks
In general, Dini gave low marks to FPGA tools. "I have no
opinion on simulation tools — there are four or five good
ones," he said. "We use two — the one from Model Tech, which
is a very good simulator, and [Simucad's] Silos, which however
has serious memory leaks."
In synthesis, Dini said he prefers Synplicity Inc.'s tools
to those from Mentor Graphics Corp., and considers Synopsys
Inc. a distant player. "It would be nice to have a tool that
would exhibit a direct correlation between ASIC synthesis and
FPGA synthesis, but Synopsys has not made that readily
available," he said. No matter what tool is chosen, Dini said
a designer should expect to spend one to three hours on
synthesis.
Regarding routing, Dini said that FPGAs route themselves
these days, unlike a couple years ago. "We find the Xilinx
parts to be slightly better at place and route than Altera's,"
he said.
Altera's SignalTap and Xilinx's ChipScope are both
acceptable in-system debugging tools, Dini said. "They
basically incorporate a logic analyzer into the design. But we
prefer to use Bridges2Silicon," a debugger from a company of
the same name. Dini said the latter tool is easier to use, but
more expensive. "No matter; you need to be aware that these
are invasive tools and adjust your designs accordingly," he
said.
Comparing Xilinx's latest Virtex II FPGA, the 2v8000, and
Altera's latest Stratix device, the 1S80, Dini said he favors
the latter. "It's the largest part in a reasonable price
range. Xilinx has priced their part as if they are not
interested in selling it," he said.
Although the Altera part has only 79,000 flip-flops
compared to 93,000 in the Xilinx 2v8000, Dini said the Altera
part has up to 1,314 available I/Os, while the Xilinx part has
1,108 I/Os and can easily fit into a 517-ball BGA. "But you
need to do the routing by hand in both parts, since the
gridded BGA is difficult to lay out," Dini said.
Saying he likes the embedded memory capacity and
multiplexers used in both parts, Dini said he prefers the 168
18-kbit memory blocks in the Xilinx part over the huge
900-kbyte total memory available in the Altera part. " That is
more than you would use in an ASIC, which is really not needed
in the FPGA," he said.
Dini feels strongly that gate counts should not be used as
a measure of FPGA capacity. "The constraining resource in
FPGAs is the number of flip-flops it has; that has to be the
criteria for what part of an ASIC can be fitted into an FPGA,"
he said.
But there are some exceptions to that rule, Dini
acknowledged, citing a microprocessor intellectual property
block containing an arithmetic logic unit as an example.
Much could be gained if a multiplier is implemented in an
FPGA, though Dini warned that operations would not be executed
as fast as they would be in an ASIC. "The rule of thumb we use
is that for equal linewidth you can run FPGAs at about
one-fifth the speed of an ASIC," he said. "With a lot of
optimization you can push that to about half that of an
ASIC."
