FPGACODE - Default PCI target source files.

fpga.v - PCI target design

pci_tar.v - pci-side data transfer
blockram.v - virtex blockram module
clocks.v - clock DCM and controls
uP_tar.v - test data from microprocessor
multiply.v - dedicated multipliers
daughter.v - daughtercard test code
dcardcap.v - capsule for daughter signals

Memory controllers:
sramctrl.v
dramctrl.v
dramset.v - dram config data from eeprom

fpga.sdc - timing constraint file
fpga.ucf - pin assignment

Test fixture:
simtar.tf
target2.tf
mt58l64l32p.v - SSRAM simulation model
mt9lsdt972.v - DRAM DIMM simulation model
mt48lc8m8a2.v - individual DRAM model
dcardsim.v - Dinigroup daughtercard model